Virtual first in first out direct memory access device

ABSTRACT

A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or saves data into the virtual FIFO, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected with the DMA unit and the processor respectively. A processor reads data from or writes data into the virtual FIFO via the virtual port and the DMA unit.

This application claims the benefit of Taiwan applications, Serial No.92134466, filed Dec. 5, 2003, and Serial No. 93137250, filed Dec. 2,2004 the subject matter of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a direct memory access (DMA) device, and moreparticularly to a virtual first in first out (FIFO) DMA device.

2. Description of the Related Art

Referring to FIG. 1, a block diagram of a conventional electronic deviceduring UART transmitting. To transmit a first data through a UART unit110, the higher layer software task 102 firstly calls a UART driver andmakes the UART driver fill the first data into a buffer 104, which canbe a ring buffer or a double buffer. When the first data has beencompletely filled into the buffer 104, the UART driver updates a bufferpointer set by the UART driver to a next address. Through the DMA unit106, the first data stored in the buffer 104 is transferred to andstored in the UART first in first out (FIFO) unit, wherein the UART unit110 serially outputs the first data. Here, the data transferring betweenthe buffer 104 and the UART FIFO unit 108 can be performed by either theDMA unit 106 or a processor. Normally, the DMA unit 106 is moreefficient in transferring data.

In a complicated electronic device, however, it is possible thatmultiple higher software layer tasks 102A and interrupt service routines(ISR) 112 might use the same UART unit 110 to transmit data, as shown inFIG. 2. Under such circumstance, the data stored in the buffer 104 mightbe overwritten, resulting in data error. If the ISR 112 has a seconddata that needs to be transmitted by the UART unit 110 when the firstdata of the higher layer software task 102A is being filled into thebuffer 104, the ISR 112 calls the UART driver to store the second datainto the buffer 104. Not until the first data of the higher layersoftware task 102A has been completely filled into the buffer 104 doesthe UART driver start to update the buffer pointer. Consequently, thesecond data is written into the buffer 104 according to original bufferpointer, and therefore the first data, which has been saved in thebuffer 104, is overwritten. After the UART driver has written the seconddata of the ISR 112 into the buffer 104, the higher layer software task102A continues to save the first data into the buffer 104 and thereforewill overwrite part of the second data. Accordingly, data loss betweenthe first data and the second data, saved in the buffer 104, will resultin data error.

There are two conventional methods of solving the data error in thebuffer 104. The first method is disabling the ISR 112 to prevent theoccurrence of data error before the higher layer software task 102Astarts to call the UART driver. However, since the ISR 112 might need tobe executed in real-time, if the system fails to process the ISR 112promptly, it will cause system error.

The second method involves the use of two buffers. Referring to FIG. 3,a block diagram of using two buffers for UART transmitting is shown. Thesecond data of the ISR 112 is saved in the buffer 104A, while the firstdata of the higher layer software task 102A is saved in the buffer 104B.By controlling the multiplexer 114, the first data and the second dataare alternately transferred to the UART FIFO unit 108 and are furthertransmitted out by the UART unit 110. However, this method requires morememory space for the buffer and the control of the UART driver is morecomplicated.

Apart from data loss and data error that might occur during UARTtransmitting, the conventional electronic device also has severalproblems during UART receiving. Referring to FIG. 4, a block diagram ofa conventional electronic device during UART receiving. After a UARTunit 410 receives a third data, the third data is temporarily stored ina UART FIFO unit 408, and then a DMA unit 406 will transfer the thirddata to a buffer 404. After the DMA unit 406 has transmitted the data ofa pre-set length to the buffer 404, the DMA unit 406 notices a processor416 to read the data stored in the buffer 404. For example, whenever theDMA unit 406 transmits data of 500 bytes to the buffer 404, the DMA unit406 notices the processor 416 to read the data stored in the buffer 404.

However, since the length of the third data received by the UART unit410 is unpredictable, the DMA unit 406 is unable to determine whetherthe third data has been completely received. For example, assume thelength of the third data is 700 bytes. After the DMA unit 406 transmitsthe first 500 bytes of the third data, the DMA unit 406 notices theprocessor 416 to read the data stored in the buffer 404. However, afterthe DMA unit 406 transmits the other 200 bytes of the third data, theDMA unit 406 will not notice the processor 416 to read the data storedin the buffer 404 because the length of received data (200 bytes of thethird data) does not reach the pre-set length and the DMA unit 406 cannot determine that the third data has been completely received.Therefore, the processor 416 has to periodically detect the status ofthe UART FIFO unit 408 so as to determine whether the UART FIFO unit 408is empty (because the data has been moved to buffer 404). Besides, theprocessor 416 further determines whether the UART FIFO unit 408 has beenin the empty status for a predetermined period. If so, it representsthat the data has been received completely. At this time, the processor406 reads the data stored in the buffer 404 to process the data.

Before the processor 416 detects the status of the UART FIFO unit 408,the processor 416 has to disable the DAM unit 406 first to preventincorrect detection due to the moving of data by the DAM unit 406.Before disabling the DAM unit 406, the UART unit 410 has to be disabledfirst and sends a signal to notice the transmitting end to cease thetransmission of data.

However, if data happens to be transmitted to the UART unit 410 when theDMA unit 406 is being disabled, the DMA unit 406 is unable to transferdata from the UART FIFO unit 408 to the buffer 404. Under thiscircumstance, the data stored in the UART FIFO unit 408 might overflow,causing data loss. To prevent data loss, a buffer of at least 16 bytesmust be reserved for the UART FIFO unit 418.

On the other hand, if the processor 416 is used to transfer data fromthe UART FIFO unit 408 to the buffer 404, the UART FIFO unit 408 must beenlarged lest the processor 416 might be frequently interrupted in orderto process data transferring because the UART FIFO unit 408 is easilyfilled up. However, this will further increase the cost.

To summarize, during UART transmitting, the UART driver of aconventional electronic device might be unable to update the bufferpointer promptly, resulting in data error as parts of data areoverwritten. During UART transmitting, (1) the processor 416 mustperiodically detect the status of the buffer 404 and the UART FIFO unit408, hence reducing the efficiency of the processor 416; (2) when theDMA unit 406 is disabled, an extra buffer of 16 bytes must be reservedfor the UART FIFO unit 408 to prevent the UART FIFO unit 408 from dataoverflow. It will consequently increase the cost and the chip size ofthe UART FIFO unit 408.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a virtual FIFO DMAdevice, which promptly updates pointer value so as to prevent data errorcaused by data overwriting during UART transmitting. According to theinvention, the UART FIFO unit does not need to reserve a space of 16bytes during UART receiving, which reduces the cost and the chip size ofthe UART FIFO unit.

According to the object of the invention, a virtual first in first out(FIFO) direct memory access (DMA) device applied in an electronic devicehaving a processor, a UART unit and a virtual FIFO is provided. Thevirtual FIFO DMA device includes a DMA unit, a virtual FIFO controllerand a virtual port. The DMA unit, which is electrically connected withthe UART unit and the virtual FIFO respectively, transfers data betweenthe UART unit and the virtual FIFO. The virtual FIFO controller, whichis electrically connected with the DMA unit, has a read pointer and awrite pointer. When DMA unit reads data from or writes data into thevirtual FIFO, the virtual FIFO controller correspondingly changes thevalue of read pointer or write pointer. The virtual port is electricallyconnected with the DMA unit and the processor respectively. Theprocessor reads data from or writes data into the virtual FIFO throughthe virtual port and the DMA unit.

According to another object of the invention, an electronic device isprovided. The electronic device includes a virtual FIFO DMA device, aUART unit, a virtual FIFO and a processor. The virtual FIFO DMA devicehas a DMA unit, a virtual port and a virtual FIFO controller, whereinthe virtual port is electrically connected with the DMA unit, while thevirtual FIFO controller, which has a read pointer and a write pointer,is electrically connected with the DMA unit. The UART unit iselectrically connected with the DMA unit, while the virtual FIFO iselectrically connected with DMA unit. The DMA unit transfers databetween the UART unit and the virtual FIFO. When DMA unit reads datafrom or writes data into the virtual FIFO, the virtual FIFO controllercorrespondingly changes the value of the read pointer or the writepointer. The processor, which is electronically connected with thevirtual port, reads data from or writes data into the virtual FIFOthrough the virtual port and the DMA unit.

Other objects, features, and advantages of the invention will becomeapparent from the following detailed description of the preferred butnon-limiting embodiments. The following description is made withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional electronic device duringUART transmitting;

FIG. 2 is a diagram showing the status when plural higher layer softwaretasks and interrupt service routines use the same UART unit to transmitdata;

FIG. 3 is a block diagram of using two virtual FIFOs for UARTtransmitting;

FIG. 4 is a block diagram of a conventional electronic device duringUART receiving;

FIG. 5 is a block diagram of a virtual FIFO DMA device according to apreferred embodiment of the invention;

FIG. 6 is a system block diagram of an electronic device using thevirtual FIFO DMA device of the invention when the UART unit performsdata receiving; and

FIG. 7 is a system block diagram of an electronic device using thevirtual FIFO DMA device of the invention when the UART unit performingdata transmitting.

DETAILED DESCRIPTION OF THE INVENTION

Different from the conventional technique, the invention applies acertain area of the memory as a virtual FIFO for replacing the UART FIFOunit in the conventional electronic device. Therefore, additional UARTFIFO unit is not required in the UART unit of the invention.Consequently, the cost and chip size of the UART unit can be reduced. Bythe invention, the processor of the electronic device can access thevirtual FIFO through the virtual FIFO DMA device with no data errorcaused by data overwriting.

Referring to FIG. 5 a block diagram of a virtual FIFO DMA deviceaccording to a preferred embodiment of the invention is shown. Thevirtual FIFO DMA device 502 according to the invention is applied in anelectronic device 500. For example, the electronic device 500 is amobile phone. The electronic device 500 includes a processor 510, a UARTunit 512 and a virtual FIFO 514. The virtual FIFO DMA device 502includes a DMA unit 504, a virtual FIFO controller 506 and a virtualport 508. The DMA unit 504, which is respectively electrically connectedwith the UART unit 512 and the virtual FIFO 514, is for transferringdata between the UART unit 512 and the virtual FIFO 514. The virtualFIFO controller 506, which is electrically connected with the DMA unit504, has a read pointer RP and a write pointer WP, for respectivelypointing to a data reading location and a data writing location. Whenthe DMA unit 504 reads data from or writes data into the virtual FIFO514, the virtual FIFO controller 506 correspondingly changes the valueof the read pointer RP or the write pointer WP. The virtual port 508 isrespectively electrically connected with the DMA unit 504 and theprocessor 510, as an accessing interface thereof. The processor 510reads data from or writes data into the virtual FIFO 514 through thevirtual port 508 and the DMA unit 504.

Referring to FIG. 6, a system block diagram of an electronic device 500using the virtual FIFO DMA device 502 of the invention when the UARTunit 512 performs data receiving is shown. In the electronic device 500,the UART unit 512 is electrically connected with the DMA unit 504; thevirtual FIFO 514 is electrically connected with the DMA unit 504; andthe processor 510 is electrically connected with the virtual port 508.The UART unit 516 has a data register 516 whose memory is one byte forinstance. After the electronic device 500 is started and before the UARTunit 512 is enabled, the processor 510 sets a certain area of a memoryas a virtual FIFO and enables the FIFO DMA device 502. The processor 510further sends a DMA setting signal DMA_set to set the initial value ofthe write pointer WP and the read pointer RP to the initial location ofthe area.

After that, the processor 510 enable UART unit 512. When the UART unit512 receives data up to one byte, the UART unit 512 sends a requestsignal DMA_req to request the DMA unit 504 to transfer (write) the datafrom the data register 516 to the location where the write pointer WPpoints in the virtual FIFO 514. Meanwhile, the DMA unit 504 sends awrite notice signal Winc to the virtual FIFO controller 506 so that thevirtual FIFO controller 506 correspondingly changes the value of thewrite pointer WP.

Besides, the processor 510 can read data stored in the virtual FIFO 514through the virtual port 508 and the DMA unit 504 at any time. Thevirtual port 508 has a peripheral device address and the processor 510takes the virtual FIFO DMA device 502 as a peripheral device. When theprocessor 510 is going to read the data in the virtual FIFO 514, theprocessor 510 sends a reading signal to the virtual port 508, so thatthe virtual port 508 sends a DMA read request REQ_R to the DMA unit 504.At this time, the DMA unit 504 reads the virtual FIFO 514 to read afirst data DATA(1) according to the read pointer RP. The DMA unit 504further sends a read notice signal Rinc to the virtual FIFO controller506, so that the virtual FIFO controller 506 changes the value of theread pointer RP accordingly. After that, the DMA unit 504 transmits thefirst data DATA(1) to the virtual port 508, which in turn transmits thefirst data DATA(1) to the processor 510.

The virtual FIFO controller 506 further has a flow control function. Thevirtual FIFO controller 506 disables all write instructions andinstructs the UART unit 512 to notice the transmitting end to cease thetransmission of data when the virtual FIFO 514 is substantially full anddisables all read instructions when the virtual FIFO 514 issubstantially empty. The virtual FIFO 514 can additionally reserve abuffer of 16 bytes to accomplish the request where the DMA unit 504still needs to transfer data from the UART unit 512 to the virtual FIFO514 when the virtual FIFO 514 is almost full but the transmitting endhas not yet ceased the transmission of data.

In the embodiment, the processor 510 accesses the virtual FIFO 514through the UART unit 512. The UART unit 512 writes data to the virtualFIFO 514 whenever the UART unit 512 receives one byte data. Therefore,despite that the UART unit 512 is unable to predict the length of thedata received and that the DMA unit 504 is unable to determine whetherthe data having a plurality of bytes has been completely received, theprocessor 510 can still access the virtual FIFO 514 through the UARTunit 512 without disabling the DMA unit 504. Furthermore, by setting acertain area of the memory as the virtual FIFO in the embodiment, theUART unit 512 does not require the UART FIFO unit of 16 bytes and thechip size of the UART unit 512 is thus reduced.

Referring to FIG. 7, a system block diagram of an electronic device 500when the UART unit 512 performs data transmitting is shown. In theelectronic device 500, when data of the processor 510 need to betransmitted by the UART unit 512, the processor 510 transmits atransmission instruction and a data-to-be-transmitted data DATA(2) tothe virtual port 508. The virtual port 508 sends a write request REQ_Wto the DMA unit 504, so that the DMA unit 504 writes the DATA(2) to thevirtual FIFO 514 according to the value of the write pointer WP.Meanwhile, the DMA unit 504 sends the write notice signal Winc to thevirtual FIFO controller 506 for the virtual FIFO controller 506 tocorrespondingly change the value of the write pointer WP. After that,the DMA unit 504 sequentially transfers the data from the virtual FIFO514 to the data register 516 of the UART unit 512.

Writing data into the virtual FIFO 514 by the processor 510, includingthe writing of data performed under the instruction of the higher layersoftware task and the ISR, is completed by the virtual FIFO DMA device502. No matter the writing of data is instructed by the higher layersoftware task or by the ISR, the processor 510 writes data into thevirtual FIFO 514 through the virtual port 508 and the DMA unit 504;meanwhile, the DMA unit 504 sends a writing notice signal Winc toinstruct the virtual FIFO controller 506 to update the value of thewrite pointer WP. According to the conventional method, the UART drivercannot update the buffer pointer until the higher layer software task orthe ISR has completed writing the data. Compared with the conventionalmethod, the virtual FIFO controller 506 according to the invention canpromptly update the value of the write pointer WP while writing datawith no data error caused by data overwriting.

Through the virtual FIFO DMA device according to the invention, the UARTdriver controls the virtual FIFO as one FIFO unit. The complexity of theUART driver is therefore reduced. Moreover, compared with theconventional method, the invention sets a certain area of memory as thevirtual FIFO and utilizes the virtual FIFO DMA device to access thevirtual FIFO. Therefore, extra UART FIFO unit is not required, and thechip size of the UART unit can be further reduced.

While the invention has been described by way of example and in terms ofa preferred embodiment, it is to be understood that the invention is notlimited thereto. On the contrary, it is intended to cover variousmodifications and similar arrangements and procedures, and the scope ofthe appended claims therefore should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements and procedures.

1. A virtual first in first out (FIFO) direct memory access (DMA) deviceapplied in an electronic device having a processor, a UART unit and avirtual FIFO, the virtual FIFO DMA device comprising: a DMA unit, beingrespectively electrically connected with the UART unit and the virtualFIFO, for transferring data between the UART unit and the virtual FIFO;a virtual FIFO controller, being electrically connected with the DMAunit, having a read pointer and a write pointer, wherein when the DMAunit reads data from or writes data into the virtual FIFO, the virtualFIFO controller correspondingly changes the value of read pointer orwrite pointer; and a virtual port, being respectively electricallyconnected with the DMA unit and the processor, wherein the processorreads data from or writes date into the virtual FIFO through the virtualport and the DMA unit.
 2. The virtual FIFO DMA device according to claim1, wherein the virtual FIFO controller has a read pointer and a writepointer for respectively pointing to a data reading location and a datawriting location of the virtual FIFO, the UART unit has a data register,when the UART unit receives data up to a particular amount, the UARTunit sends a request signal to request the DMA unit to transfer the datafrom the data register to the location where the write pointer WP pointsin the virtual FIFO, the DMA unit further sends a write notice signal tothe virtual FIFO controller so that the virtual FIFO controllercorrespondingly changes the value of the write pointer; wherein thevirtual port has a peripheral device address and the processor takes thevirtual FIFO DMA device as a peripheral device, when the processor readsthe data in the virtual FIFO, the processor sends a reading signal tothe virtual port and the virtual port sends a DMA read request to theDMA unit, the DMA unit reads the virtual FIFO to get a first dataaccording to the read pointer, the DMA unit further sends a read noticesignal to the virtual FIFO controller to change the value of the readpointer accordingly, the DMA unit transmits the first data to thevirtual port, which in turn transmits the first data to the processor.3. The virtual FIFO DMA device according to claim 1, wherein theelectronic device is a mobile phone.
 4. The virtual FIFO DMA deviceaccording to claim 1, wherein the virtual FIFO controller has a readpointer and a write pointer for respectively pointing to a data readinglocation and a data writing location of the virtual FIFO, the UART unithas a data register, when data of the processor need to be transmittedfrom the UART unit, the processor transmits a transmission instructionand a data-to-be-transmitted data to the virtual port, the virtual portsends a write request to the DMA unit, and the DMA unit writes thedata-to-be-transmitted data to the virtual FIFO according to the valueof the write pointer, the DMA unit sends a write notice signal to thevirtual FIFO controller for the virtual FIFO controller tocorrespondingly change the value of the write pointer, the DMA unitsequentially transfers the data from the virtual FIFO to the dataregister of the UART unit.
 5. The virtual FIFO DMA device according toclaim 1, wherein the virtual port has a peripheral device address andthe processor takes the virtual FIFO DMA device as a peripheral device,when the processor reads data from the virtual port, the virtual portsends a DMA read request to the DMA unit, which in turn gets a firstdata from the virtual FIFO according to the read pointer, the virtualFIFO controller changes the value of the read pointer accordingly, theDMA unit transmits the first data to the virtual port, which in turntransmits the first data to the processor; when the processor transmitsa to-be-written second data to the virtual port, the virtual port sendsa DMA write request to the DMA unit, which in turn writes the seconddata into the virtual FIFO according to the write pointer, the virtualFIFO controller changes the value of the write pointer.
 6. The virtualFIFO DMA device according to claim 1, wherein the virtual FIFOcontroller further has a flow control function, and the virtual FIFOcontroller disables all write instructions when the virtual FIFO issubstantially full, and disables all read instructions when the virtualFIFO is substantially empty.
 7. An electronic device, comprising: avirtual FIFO DMA device, comprising: a DMA unit; a virtual port, beingelectrically connected with DMA unit; and a virtual FIFO controller,being electrically connected with the DMA unit, having a read pointerand a write pointer; a UART unit, being electrically connected with theDMA unit; a virtual FIFO, being electrically connected with the DMAunit, wherein the DMA unit transfers data between the UART unit and thevirtual FIFO, and the virtual FIFO controller correspondingly changesthe value of the read pointer or the write pointer when the DMA unitreads data from or writes data into the virtual FIFO; and a processor,being electrically connected with virtual port, wherein the processorreads data from or writes data into the virtual FIFO through the virtualport and the DMA unit.
 8. An electronic device according to claim 7,wherein the UART unit has a data register, and data of the data registeris transferred to the virtual FIFO by the DMA unit when the dataregister is full.
 9. The virtual FIFO DMA device according to claim 8,wherein the electronic device is a mobile phone.
 10. The virtual FIFODMA device according to claim 7, wherein the virtual port has aperipheral device address, and the processor takes the virtual FIFO DMAdevice as a peripheral device, when the processor reads data from thevirtual port, the virtual port sends a DMA read request to the DMA unit,which in turn reads a first data from the virtual FIFO according to theread pointer, the virtual FIFO controller changes the value of the readpointer accordingly, the DMA unit transmits the first data to thevirtual port, which in turn transmits the first data to the processor;when the processor transmits a to-be-written second data to the virtualport, the virtual port sends a DMA write request to the DMA unit, whichin turn writes the second data into the virtual FIFO according to thewrite pointer, the virtual FIFO controller changes the value of thewrite pointer.
 11. The virtual FIFO DMA device according to claim 7,wherein the virtual FIFO controller further has a flow control function,and the virtual FIFO controller disables all write instructions when thevirtual FIFO is substantially full and disables all read instructionswhen the virtual FIFO is substantially empty.
 12. A virtual first infirst out (FIFO) direct memory access (DMA) method applied in a virtualFIFO DMA device of an electronic device, the electronic device having aprocessor, a UART unit and a virtual FIFO, the FIFO DMA device having aDMA unit, a virtual FIFO controller, and a virtual port, the virtualFIFO controller having a read pointer and a write pointer, the UART unithaving a data register, the virtual port having a peripheral deviceaddress, and the processor taking the virtual FIFO DMA device as aperipheral device, the virtual FIFO DMA method comprising: when the UARTunit receives data up to a particular amount, the UART unit sending arequest signal to request the DMA unit to transfer the data from thedata register to the location where the write pointer WP points in thevirtual FIFO, the DMA unit further sending a write notice signal to thevirtual FIFO controller so that the virtual FIFO controllercorrespondingly changes the value of the write pointer; when theprocessor reads the data in the virtual FIFO, the processor sending areading signal to the virtual port and the virtual port sending a DMAread request to the DMA unit, the DMA unit reading the virtual FIFO toget a first data according to the read pointer, the DMA unit furthersending a read notice signal to the virtual FIFO controller so that thevirtual FIFO controller changes the value of the read pointeraccordingly, the DMA unit transmitting the first data to the virtualport, which in turn transmits the first data to the processor; when dataof the processor need to be transmitted by the UART unit, the processortransmitting a transmission instruction and a data-to-be-transmitteddata to the virtual port, the virtual port sending a write request tothe DMA unit and the DMA unit writing the data-to-be-transmitted data tothe virtual FIFO according to the value of the write pointer, the DMAunit sending a write notice signal to the virtual FIFO controller forthe virtual FIFO controller to correspondingly change the value of thewrite pointer, the DMA unit sequentially transferring the data from thevirtual FIFO to the data register of the UART unit.
 13. The virtual FIFODMA device according to claim 12, wherein the electronic device is amobile phone.